Microelectronic devices, such as micro-scale electronic, electro-mechanical or optical devices are generally fabricated on and/or in work pieces or substrates, such as silicon wafers. In a typical fabrication process, for example on a semiconductor material wafer, a conductive seed layer is first applied onto the surface of the substrate using chemical vapor deposition (CVD), physical vapor deposition (PVD), electro less plating processes, or other suitable methods. After forming the seed layer, a blanket layer or patterned layer of metal is plated onto the substrate by applying an appropriate electrical potential between the seed layer and one or more electrodes in the presence of an electro processing solution containing metal ions. The substrate is then cleaned, etched and/or annealed in subsequent procedures, to form devices, contacts or conductive lines. Some substrates may have a barrier layer with the seed layer formed on the barrier layer.
Currently, most micro-electronic devices are made on substrates plated with copper. Although copper has high conductivity, it typically requires a barrier layer such as tantalum nitride (TaN) to prevent diffusion of copper into the substrate or dielectric material on the substrate. These types of barrier layer have relatively low conductivity. Using known techniques, features on the substrate are filled with electroplated copper using acid copper chemistries or electroplating solutions. These chemistries often use additives to promote a super conformal fill process (with the features filling primarily from the bottom up, rather than inwardly from the sides) and create a void-free fill. As the feature sizes shrink, achieving void free fill with the traditional copper plating processes has become more difficult. Also as the features get smaller, the barrier layer required for copper occupies a larger volume, because a minimum barrier layer thickness must be maintained to prevent copper diffusion, regardless of feature size.
For example if a minimum barrier layer thickness of 3 nm is required to prevent diffusion of copper, then for a feature having a 60 nm critical dimension with an aspect ratio of 4:1, the barrier layer occupies roughly 11% of the cross-sectional area. However, with a feature a having a 20 nm critical dimension with an aspect ratio of 2:1, the barrier layer must remain 3 nm thick, but it now occupies 33% of the cross sectional area. In this case the volume of the barrier layer (which has low conductivity) is proportionally higher, so the resistance of the interconnect, via or other feature is proportionally higher. With progressively smaller features, the proportion of copper to barrier layer increases, to the extent that the resistance becomes unacceptable.
One approach proposed for overcoming this technical challenge is to replace copper with a metal that does not require a barrier layer, such as cobalt. Although cobalt has a higher resistance than copper (6 uOhm-cm for cobalt versus 2 uOhm-cm for copper), cobalt does not require a barrier layer because it does not diffuse into the silicon or dielectric. U.S. Patent Application Publication No. 20130260555 describes filling large and small features by applying cobalt via CVD. Although this method works well for smaller features, e.g., of 7-10 nm, CVD is not well suited for filling features larger than about 10 nm. Improved techniques are needed.